Japanese researchers have developed a compact model for circuit simulation to predict the circuit behavior of tunnel field-effect transistors (tunnel FETs). This device-operation model simulates current–voltage characteristics by predicting the electric field distribution in a tunnel FET and estimating the tunnel current. It is described in Verilog-A language and therefore can be incorporated into existing major circuit simulators. The model is expected to contribute to the design of tunnel FETs aiming at the realization of ultra-low-power circuits.
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